In a semiconductor device, which has a semiconductor die having an integrated circuit thereon, it is well known to have an ESD circuit to protect the input/output signal of the integrated circuit from electrostatic discharge. Typically, the ESD circuit is integrated with the integrated circuit onto the same single semiconductor die.
In U.S. Pat. Nos. 6,198,136 and 6,066,890, the references disclose the ESD circuit being a separate circuit apart from a semiconductor die and packaged together in a single package to protect and enhance the performance of the integrated circuit die. See, for example, FIGS. 3-5 and column 3, lines 29-50 of U.S. Pat. No. 6,066,890. However, one of the shortcomings of these references is that the particular order by which the external leads are bonded or connected to the various circuits is not disclosed. This is important in that since the ESD circuit is removed from the integrated circuit die, the die is “exposed” to the harmful effects of ESD, during the bonding process.
Further, the references do not disclose particular structures of chip carriers and semiconductor dies that may be connected to the separate ESD circuit advantageously. In particular, such a structure would be useful for packaging a semiconductor die with the integrated circuit as memory circuits. Finally, the references do not disclose the use of separate ESD circuits with terminating resistors outside of the semiconductor die but part of the package of the semiconductor device. These and other shortcomings are overcome by the present invention.
Other relevant art includes U.S. Pat. Nos. 5,771,140; 6,385,021; and 5,859,758.